The transmission of digital data is necessary in a great number of systems in which a central station or unit, such as a central processing unit or a central control unit, for example, must exchange data with one or more peripheral modules. In order to achieve this, bus systems are typically used, over which the individual data units are transmitted at a certain prescribed clock frequency. In order that a peripheral module can properly receive and recognize without errors the digital data transmitted by the central unit, it is necessary that the peripheral module accepts the incoming data at the same clock frequency at which the data were transmitted.
In order to ensure that the central unit and the peripheral modules operate with the same clock frequency for carrying out a data exchange, it is known to use highly exactly operating clock signal generators with mutually matched clock frequencies in the central unit as well as in the peripheral modules. However, such highly accurate clock signal generators require high precision components, such as quartz crystal oscillators, for example, in order to very precisely maintain the clock frequency at a constant value even over a long period of time. For this reason, such highly accurate clock signal generators are relatively complicated and expensive. Furthermore, even such clock signal generators can drift or become unsynchronized from one another over time.
Other systems for synchronizing the data acceptance or pulse frame clock cycle are known, for example as described in German Patent Publication 2,657,365 B1 and in U.S. Pat. No. 4,988,989. Therein, in order to achieve a time-matching of the transmitting cycle with the receiving cycle, a synchronization pulse or synchronization pulse train having a known form, for example, having known signal level variations, is periodically transmitted. Moreover, U.S. Pat. No. 4,988,989 describes a master-slave communication system in which an initiallizing data signal activates a separate timer provided in the slave. In this manner, a time synchronized sampling of the subsequently transmitted data is made possible. German Patent Publication 2,657,365 B1 describes a method for frame synchronization of a time division multiplexing system in which the counters are correspondingly reset with reference to a synchronization recognition signal and thereby a synchronization is achieved. It is also known to use a synchronizing word comprising a plurality of low and high signal levels, for achieving a synchronization.
Moreover, it is also known to use coding methods, such as the Manchester process for example, in which the clock cycle information can be recovered.
Another possibility for assuring the same clock frequency in the central unit and in the peripheral modules is to connect all of the peripheral modules with the central unit over respective additional clock conductors or lines. However, the provision of such additional clock lines for ensuring a common synchronous system clock signal becomes extremely complicated and costly, especially in systems in which a central control device must exchange data with a plurality of decentralized or peripheral modules, such as in decentralized safety systems in motor vehicles. Moreover, motor vehicle safety systems are becoming ever more complex along with the increasing requirements for increased safety for occupants of the vehicle. Thus, as more safety systems, such as for example side air bags and the like, are being called for in addition to a driver side air bag, a passenger side air bag, seat belt tensioners, roll-over bars, and the like, correspondingly also the number of required peripheral modules and thus also the number of the end stages for triggering or activating the individual safety systems is increasing considerably. As a result of this increasing complexity and number of end stages in a vehicular safety system, the known data bus systems either require a correspondingly increased number of the above described highly accurate and expensive clock signal generators, or the assembly and installation of the system becomes ever more complex and costly in view of the installation of separate clock cycle lines connecting the central unit with the peripheral modules.